Energy Efficient Low Complexity Inexact Adder for Error Tolerant Applications

Author:

Guduru Tharun Kumar1,Kumar Avula Manoj1,Esakki Papanasam1,Nagarajan Manikandan2

Affiliation:

1. School of Electronics, Vellore Institute of Technology Chennai Campus,India

2. SASTRA Deemed university,School of computing,Thanjavur,India

Publisher

IEEE

Reference15 articles.

1. Low-power, High-speed 1- bit Inexact Full Adder Cell Designs Applicable to Low-energy Image Processing;zareei;International Journal of Electronics,2018

2. Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

3. Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications

4. An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

5. Fixed Point Multi-bit Approximate Adder Based Convolutional Neural Network Accelerator for Digit Classification Inference;manikandan,2020

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Area Efficient Energy Saving Inexact Multiplier for Error Resilient Applications;2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON);2022-11-26

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