Author:
Rao M. Rajeswara,Sharma R. K.
Cited by
7 articles.
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1. Area-Optimized FPGA Accelerator for High Throughput Encryption with AXI Integration;2024 International Telecommunications Conference (ITC-Egypt);2024-07-22
2. A Novel Approach to AES S-BOX and Inverse S-BOX Design on FPGA Devices;2023 11th International Japan-Africa Conference on Electronics, Communications, and Computations (JAC-ECC);2023-12-18
3. An Efficient Implementation of AES algorithm using Custom Key;2022 International Conference on Intelligent Innovations in Engineering and Technology (ICIIET);2022-09-22
4. Methods for improving the implementation of advanced encryption standard hardware accelerator on field programmable gate array‐A survey;SECURITY AND PRIVACY;2022-07-17
5. Advanced Encryption Standard Algorithm with Optimal S-box and Automated Key Generation;2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE);2022-04-28