FPGA Implementation of FEC Encoder with BCH & LDPC Codes for DVB S2 System

Author:

Digdarsini Durga,Mishra Deepak,Mehta Sanjay,Ram T.V.S.

Publisher

IEEE

Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Model based design of DVB S2 Transmitter and realization on SDR platform;2023 9th International Conference on Smart Computing and Communications (ICSCC);2023-08-17

2. VLSI Implementation of Error Correction Codes for Molecular Communication;Wireless Personal Communications;2023-04-05

3. Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry;IEEE Access;2023

4. Low-Complexity Parallel Syndrome Computation for BCH Decoders Based on Cyclotomic FFT;2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2022-11-11

5. Performance Evaluation of Multilevel Coded FEC with Register-Transfer-Level Emulation;2022 27th OptoElectronics and Communications Conference (OECC) and 2022 International Conference on Photonics in Switching and Computing (PSC);2022-07-03

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