On the generation of area-time optimal testable adders-Reference-Cited by-同舟云学术

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On the generation of area-time optimal testable adders

Published:1995 Issue:9 Volume:14 Page:1049-1066
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Becker B.,Drechsler R.,Molitor P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx1/43/9136/00406707.pdf?arnumber=406707

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Concurrent Error Detectable Carry Select Adder with Easy Testability;IEEE Transactions on Computers;2019-07-01

2. Real-time fault-tolerance with hot-standby topology for conditional sum adder;Microelectronics Reliability;2015-02

3. A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier;IEICE Transactions on Information and Systems;2010

4. Level-Testability of Multi-operand Adders;2008 17th Asian Test Symposium;2008-11

5. Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units;IEEE Transactions on Computers;2006-11

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