Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs
Author:
Affiliation:
1. National Yang Ming Chiao Tung University
2. Realtek Semiconductor Corporation
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9806045/9806137/09806225.pdf?arnumber=9806225
Reference11 articles.
1. Machine learning and systems for building the next generation of EDA tools
2. Timing Verification and the Timing Analysis program
3. A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist;tabrizi;55th ACM/IEEE Design Automation Conference,2018
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A Deep Learning Model for Pre-Routing Path Delay Prediction in VLSI Based on Subpath;2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE);2024-05-24
2. Performance (Timing) Analysis;FPGA EDA;2024
3. Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops;2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI);2023-06-20
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