A Cost-efficient Hardware Accelerator Design for 2D Sliding Discrete Fourier Transform
Author:
Affiliation:
1. National Formosa University,Computer Science and Information Engineering,Taiwan
2. National Formosa University,Department of Electro-Optical Engineering,Taiwan
3. National Formosa University,Department of Automation Engineering,Taiwan
Funder
Ministry of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10226627/10226615/10227037.pdf?arnumber=10227037
Reference3 articles.
1. Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms
2. A Non-Feedback-Loop and Low-Computation- Complexity Algorithm Design for a Novel 2-D Sliding DFT Computation
3. 2D Discrete Fourier Transform on Sliding Windows
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