The inference operation optimization of an improved LeNet-5 convolutional neural network and its FPGA hardware implementation
Author:
Affiliation:
1. South China Agricultural University,College of Electronic Engineering (College of Artificial Intelligence),Guangzhou,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10053086/10053095/10053198.pdf?arnumber=10053198
Reference9 articles.
1. A scalable and efficient convolutional neural network accelerator using HLS for a system-on-chip design
2. Optimizing convolutional neural networks on multi-core vector accelerator
3. Briefly Analysis about CNN Accelerator based on FPGA
4. Performance comparison of CNN, QNN and BNN deep neural networks for real-time object detection using ZYNQ FPGA node
5. Reconfigurable and hardware efficient adaptive quantization model-based accelerator for binarized neural network[J];sasikumar;Computers and Electrical Engineering,2022
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1. Hardware accelerator for high accuracy sign language recognition with residual network based on FPGAs;IEICE Electronics Express;2024-02-25
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