An FDD Auxiliary Receiver with a Highly Linear Low Noise Amplifier
Author:
Affiliation:
1. National ASIC System Engineering Research Center, Southeast University,Nanjing,China
2. University of Pavia,Department of Electrical, Computer and Biomedical Engineering,Pavia,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9911257/9911222/09911524.pdf?arnumber=9911524
Reference14 articles.
1. A Quantized Analog RF Front End
2. 24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radio
3. 6.5 A 3dB-NF 160MHz-RF-BW Blocker-Tolerant Receiver with Third-Order Filtering for 5G NR Applications
4. Tunable Blocker-Tolerant On-Chip Radio-Frequency Front-End Filter With Dual Adaptive Transmission Zeros for Software-Defined Radio Applications
5. A Blocker-Tolerant RF Front End With Harmonic-Rejecting $N$ -Path Filter
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1. Interferer-Tolerant RX Front-End Architectures;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
2. A mm-Wave Blocker-Tolerant Receiver Achieving <4 dB NF and −3.5 dBm B1dB in 65-nm CMOS;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11
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