Novel high speed vedic mathematics multiplier using compressors
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6520973/6526372/06526456.pdf?arnumber=6526456
Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications;Scientific Reports;2023-12-16
2. 32-Bit RISC Processor Using VedicMultiplier;2022 3rd International Conference for Emerging Technology (INCET);2022-05-27
3. Power and Area efficient VLSI architecture implementation of Adaptive Recursive Karatsuba with reversible SRCSLA;INT J EARLY CHILD SP;2022
4. High speed Power efficient Vedic arithmetic modules on Zedboard‐Zynq‐7000 FPGA;International Journal of Circuit Theory and Applications;2021-08-26
5. VLSI Implementation of Vedic Multiplier;Design and Development of Efficient Energy Systems;2021-04-15
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