Automated Custom Instruction Generation for Domain-Specific Processor Acceleration

Author:

Clark N.T.,Hongtao Zhong ,Mahlke S.A.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 57 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. DAG Processing Unit Version 2 (DPU-v2): Efficient Execution of Irregular Workloads on a Spatial Datapath;Efficient Execution of Irregular Dataflow Graphs;2023

3. DPU-v2: Energy-efficient execution of irregular directed acyclic graphs;2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO);2022-10

4. NOVIA: A Framework for Discovering Non-Conventional Inline Accelerators;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17

5. ISAMod: A Tool for Designing ASIPs by Comparing Different ISAs;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02

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