A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology-Reference-Cited by-同舟云学术

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A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology

Published:2019-08 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE Hot Chips 31 Symposium (HCS)
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Author:

Venkatesan Rangharajan,Shao Yakun Sophia,Zimmer Brian,Clemons Jason,Fojtik Matthew,Jiang Nan,Keller Ben,Klinefelter Alicia,Pinckney Nathaniel,Raina Priyanka,Tell Stephen G.,Zhang Yanqing,Dally William J.,Emer Joel S.,Gray C. Thomas,Keckler Stephen W.,Khailany Brucek

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8869546/8875627/08875657.pdf?arnumber=8875657

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Correct-by-Construction Design of Custom Accelerator Microarchitectures;IEEE Transactions on Computers;2024-01

2. Machine Learning Hardware Design for Efficiency, Flexibility, and Scalability [Feature];IEEE Circuits and Systems Magazine;2023

3. Behavioral Analytics of Consumer Complaints;Advances in Business Information Systems and Analytics;2022-08-12

4. MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units;ACM Transactions on Design Automation of Electronic Systems;2022-06-06

5. Brain-inspired computing needs a master plan;Nature;2022-04-13

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