A 9V-Tolerant 71.4%-Efficiency Stacked-Switched-Capacitor Stimulation System with Level-Adaptive Switching Control and Rapid Stimulus-Synchronized Charge Balancing

Author:

Park Minju1,Eom Kyeongho1,Lee Han-Sol1,Ku Seung-Beom1,Lee Hyung-Min1

Affiliation:

1. Korea University,School of Electrical Engineering,Seoul,Korea

Funder

Ministry of Health

Publisher

IEEE

Reference6 articles.

1. A 12-V Single-Input Multiple-Independently ConfigurableOutput Dynamic Voltage Scaling Supply in Standard 0.18-?m CMOS for Electrical Stimulation Applications;zeng;IEEE SSC,2022

2. A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

3. A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression

4. A 22 V Compliant 56?W Twin-Track Active Charge Balancing Enabling 100 Charge Compensation Even in Monophasic and 36 Amplitude Correction in Biphasic Neural Stimulators;butz;IEEE JSSC,2018

5. A Trimodal Wireless Implantable Neural Interface Systemon-Chip;jia;IEEE ISSCC,2020

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