A 9V-Tolerant 71.4%-Efficiency Stacked-Switched-Capacitor Stimulation System with Level-Adaptive Switching Control and Rapid Stimulus-Synchronized Charge Balancing
Author:
Affiliation:
1. Korea University,School of Electrical Engineering,Seoul,Korea
Funder
Ministry of Health
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121236.pdf?arnumber=10121236
Reference6 articles.
1. A 12-V Single-Input Multiple-Independently ConfigurableOutput Dynamic Voltage Scaling Supply in Standard 0.18-?m CMOS for Electrical Stimulation Applications;zeng;IEEE SSC,2022
2. A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
3. A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression
4. A 22 V Compliant 56?W Twin-Track Active Charge Balancing Enabling 100 Charge Compensation Even in Monophasic and 36 Amplitude Correction in Biphasic Neural Stimulators;butz;IEEE JSSC,2018
5. A Trimodal Wireless Implantable Neural Interface Systemon-Chip;jia;IEEE ISSCC,2020
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 3.3-to-11V-Supply-Range 10μW/Ch Arbitrary-Waveform-Capable Neural Stimulator with Output-Adaptive-Self-Bias and Supply-Tracking Schemes in 0.18μm Standard CMOS;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
2. A Fully Integrated Dynamic-Voltage-Scaling Stimulator IC with Miniaturized Reconfigurable Supply Modulator and Channel Drivers for Cochlear Implants;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21
3. A 9-V-Tolerant Stacked-Switched-Capacitor Stimulation System With Level-Adaptive Switch Control and Rapid Stimulus-Synchronized Charge Balancing for Implantable Devices;IEEE Journal of Solid-State Circuits;2023
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