DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET
Author:
Affiliation:
1. Princeton University
2. Columbia University
3. University of California,Santa Barbara
Funder
Air Force Research Laboratory
Advanced Research Projects Agency
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121257.pdf?arnumber=10121257
Reference9 articles.
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
2. MuchiSim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems;2024 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2024-05-05
3. 14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
4. AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
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