Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications-Reference-Cited by-同舟云学术

Incorporating Bottom-Up Approach Into Device/Circuit Co-Design for SRAM-Based Cache Memory Applications

Published:2022-11 Issue:11 Volume:69 Page:6127-6132
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Tayal Shubham¹^ORCID,Smaani Billel²,Rahi Shiromani Balmukund³,Upadhyay Abhishek Kumar⁴^ORCID,Bhattacharya Sandip⁵^ORCID,Ajayan J.⁵^ORCID,Jena Biswajit⁶^ORCID,Myeong Ilho⁷^ORCID,Park Byung-Gook⁷^ORCID,Song Young Suh⁷^ORCID

Affiliation:

1. A&MS Layout Design Engineer, Synopsys India Pvt. Ltd., Hyderabad, India

2. Centre Universitaire Abdelhafid Boussouf, Mila, Algeria

3. Department of Electrical Engineering, Indian Institute of Technology, Kanpur, India

4. X-FAB Dresden GmbH & Co. KG, Dresden, Germany

5. Department of Electronics and Communication Engineering, SR University, Warangal, India

6. School of Electronics Engineering, Vellore Institute of Technology, Chennai, India

7. Inter-University Semiconductor Research Center (ISRC), Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/9926983/09915485.pdf?arnumber=9915485

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