Intrablock Wear Leveling to Counter Layer-to-Layer Endurance Variation of 3-D NAND Flash Memory
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, The University of Alabama in Huntsville, Huntsville, AL, USA
Funder
National Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://ieeexplore.ieee.org/ielam/16/10004030/9966490-aam.pdf
Reference17 articles.
1. Mitigating Pillar-to-Pillar Variability of Ground Select Transistor in 3-D NAND Flash Memory
2. The Effects of Taper-Angle on the Electrical Characteristics of Vertical NAND Flash Memories
3. A Rigorous 3-D NAND Flash Cost Analysis
4. Layer-Dependent Bit Error Variation in 3-D NAND Flash Under Ionizing Radiation
5. Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations
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1. Life-after-Death: Exploring Thermal Annealing Conditions to Enhance 3D NAND SSD Endurance;Proceedings of the 16th ACM Workshop on Hot Topics in Storage and File Systems;2024-07-08
2. Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-05
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