Modeling and Characterization of Annealing-Induced Cu Protrusion of TSVs With Polyimide Liner Considering Diffusion Creep Behavior
Author:
Affiliation:
1. School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing, China
2. BIT Chongqing Center for Microelectronics and Microsystems, Chongqing, China
Funder
National Natural Science Foundation of China
Beijing Nova Programof Science and Technology
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10025571/09994657.pdf?arnumber=9994657
Reference34 articles.
1. Modeling creep and fatigue of copper alloys
2. Through-silicon via stress characteristics and reliability impact on 3D integrated circuits
3. Failure mechanisms and optimum design for electroplated copper through-silicon vias (TSV);liu;Proc 59th Electron Compon Technol Conf,2009
4. Predicting plated-through-hole reliability in high temperature manufacturing processes
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1. General Analytical Method for Investigating Parasitic Characteristics of Through Glass Vias (TGVs) in 3-D Integration;IEEE Transactions on Electron Devices;2023-09
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