Cointegration of the TFT-Type AND Flash Synaptic Array and CMOS Circuits for a Hardware-Based Neural Network
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
2. School of Electrical Engineering, Kookmin University, Seoul, South Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10004030/09955410.pdf?arnumber=9955410
Reference18 articles.
1. A Comprehensive Modeling Framework for Ferroelectric Tunnel Junctions
2. Nanoelectronic Programmable Synapses Based on Phase Change Materials for Brain-Inspired Computing
3. Si-Based FET-Type Synaptic Device With Short-Term and Long-Term Plasticity Using High- $\kappa$ Gate-Stack
4. Field Effect Transistor-Type Devices Using High-κ Gate Insulator Stacks for Neuromorphic Applications
5. Binary neural network with 16 Mb RRAM macro chip for classification and online training
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1. NOR-Type Flash Array Based on Four-Terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling;IEEE Electron Device Letters;2024-06
2. Neurons With Captive Synaptic Devices for Temperature Robust Spiking Neural Networks;IEEE Electron Device Letters;2024-03
3. Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training;Advanced Electronic Materials;2024-01-08
4. Analysis Method of Dynamic Read Variation in a TFT-Type Synaptic Devices With Poly-Si Channel Structure;IEEE Transactions on Electron Devices;2024
5. A Quantized-Weight-Splitting Method of RRAM Arrays for Neuromorphic Applications;IEEE Access;2024
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