HV-LDMOS Device Engineering Insights for Moving Current Filament to Enhance ESD Robustness
Author:
Affiliation:
1. Department of Electronic Systems Engineering, Indian Institute of Science, Bengaluru, India
2. Analog Technology Development, Texas Instruments, Dallas, TX, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9722602/09691466.pdf?arnumber=9691466
Reference22 articles.
1. Performance and Reliability Co-design of LDMOS-SCR for Self-Protected High Voltage Applications On-Chip
2. ESD robust DeMOS devices in advanced CMOS technologies;shrivastava;Proc EOS/ESD Symp,2011
3. Effects of Background Doping Concentration on ESD Protection Properties of High Voltage Operation Extended Drain N-Type MOSFET Device
4. Engineering optimal high current characteristics of high voltage DENMOS
5. The influence of the layout on the ESD performance of HV-LDMOS;lee;Proc 22nd Int Symp Power Semiconductor Device IC’s (ISPSD),2010
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1. High-Voltage ESD Protection Devices With High Robustness of 13 kV and Strong Radiation Tolerance up to 200 krad(Si);IEEE Transactions on Electron Devices;2024-06
2. ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation;2022 IEEE International Conference on Consumer Electronics - Taiwan;2022-07-06
3. Robust HV Power pLDMOS Components for ESD Protection by the Drain-side Parasitic Schottky Diode and SCR Engineering;2022 International Power Electronics Conference (IPEC-Himeji 2022- ECCE Asia);2022-05-15
4. An ESD Investigation of 100 V UHV nLDMOSs Embedded with Schottky/SCR in the Drain Side;2022 8th International Conference on Applied System Innovation (ICASI);2022-04-22
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