An Island Drain Double-Gate DeMOS With Self-Aligned Sub-Gate to Achieve Multifold Transient Frequency Enhancement
Author:
Affiliation:
1. Department of Electrical Engineering, IIT Bombay, Mumbai, India
2. Intel Deutschland, Neubiberg, Germany
Funder
Nanoelectronics Network for Research and Application (NNetRA), India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/9864631/09842367.pdf?arnumber=9842367
Reference31 articles.
1. OFF-state degradation and correlated gate dielectric breakdown in high voltage drain extended transistors: A review
2. Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device
3. Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness
4. A Novel Trench-Gated Power MOSFET With Reduced Gate Charge
5. Novel 5V-EDMOS transistor with a record /max of 450 GHz in a baseline 40 nm CMOS technology;dinh;IEDM Tech Dig,2017
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