Leakage Reduction on Universal Gates Using ONOFIC Technique-Reference-Cited by-同舟云学术

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Leakage Reduction on Universal Gates Using ONOFIC Technique

Published:2024-04-18 Issue: Volume:6 Page:1-5
ISSN:
Container-title:2024 International Conference on E-mobility, Power Control and Smart Systems (ICEMPS)
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Author:

Bose Anitha P¹,Santhi N¹

Affiliation:

1. Noorul Islam Centre For Higher Education,Department of ECE

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10559243/10559244/10559323.pdf?arnumber=10559323

Reference17 articles.

1. Low Power VLSI Design Techniques: A Review

2. An Investigation of Low Power VLSI Design Techniques;Kumar;Journal of Science, Computing and Engineering Research,2023

3. Performance of leakage power minimization technique for cmos vlsi technology;Tharaneeswaran;Ictact journal on communication technology,2012

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