A Low Phase Noise Programmable Divider Operating at 24GHz in a 65-nm CMOS Technology-Reference-Cited by-同舟云学术

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A Low Phase Noise Programmable Divider Operating at 24GHz in a 65-nm CMOS Technology

Published:2023-05 Issue: Volume: Page:
ISSN:
Container-title:2023 2nd International Joint Conference on Information and Communication Engineering (JCICE)
language:
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Author:

Jiang Ruifeng¹,Lei Yulong¹,Ye Song¹,He Chao¹,Li Caihong¹,Wang Wenhao¹

Affiliation:

1. Chengdu University of Information Technology,College of communication Engineering,Chengdu,China

Funder

Chengdu University

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10217212/10217258/10217279.pdf?arnumber=10217279

Reference10 articles.

1. On Certain Integrals Of Lipschitz-Hankel Type Involving Products Of Bessel Functions;eason;Phil Trans Roy Soc London,1955

2. A Programmable Frequency Divider With a Full Modulus Range and 50% Output Duty Cycle

3. A 3–10mW, 3.1–10.6GHz integer-N QPLL with reference spur reduction technique for UWB-based cognitive radios

4. A Low Power Multi-Modulus Programmable Divider with TSPC Technology

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1. New Programmable LFSR Counters with Automatic Encoding and State Extension;Electronics;2024-01-18

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