FPGA-Oriented Target Detection Accelerator Design
Author:
Affiliation:
1. Harbin University of Science and Technology,School of Measurement and Control Technology and Communication Engineering,Harbin,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10455087/10454140/10455842.pdf?arnumber=10455842
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4. A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing
5. Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding;Han;arXiv preprint arXiv:1510.00149,2015
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