1. CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-02
2. Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis;2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD);2021-11-01
3. Area-Optimal Transistor Folding for 1-D Gridded Cell Design;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2013-11
4. A New Transistor-Level Layout Generation Strategy for Static CMOS Circuits;2006 13th IEEE International Conference on Electronics, Circuits and Systems;2006-12
5. Analytical approach to layout generation of datapath cells;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2002-12