Area and Power Efficient Design of Novel Karatsuba Double MAC (K-DMAC)

Author:

Laxman Amgoth1,Reddy N. Siva Sankar2,Naik B. Rajendra3

Affiliation:

1. College of Engineering, Osmania University,ECE Dept.,Hyderabad,Telangana,India

2. Vasavi College of Engineering,Hyderabad,Telangana,India

3. College of'Engineering, Osmania University,Hyderabad,Telangana,India

Publisher

IEEE

Reference27 articles.

1. 14.6 a 0.62mwultra-Iow-power convolutional- neuralnetwork face-recognition processor and a CIS integrated with always-on haar-like face detector;bong;2017 IEEE International Solid-State Circuits Conference (ISSCC),0

2. Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. VLSI Implementation of Modified Karatsuba Multiplier for Low Power Applications;2024 International Conference on Smart Systems for Electrical, Electronics, Communication and Computer Engineering (ICSSEECC);2024-06-28

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