Author:
Georgoulopoulos Nikolaos,Hatzopoulos Alkiviadis
Cited by
4 articles.
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1. Design and Verification of a SAR ADC SystemVerilog Real Number Model;Journal of Electronic Testing;2024-06
2. System Verilog Real Number Modelling for 8-bit Flash ADC and R2R DAC;2024 International Conference on Automation and Computation (AUTOCOM);2024-03-14
3. Real Number Modeling of a SAR ADC behavior using SystemVerilog;2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2022-06-12
4. Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog;Journal of Electronic Testing;2021-12