Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training

Author:

Millican Spencer,Sun Yang,Roy Soham,Agrawal Vishwani

Publisher

IEEE

Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A High Performance PODEM Algorithm with the Improved Backtrace Process;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

2. Test Point Selection for Multi-Cycle Logic BIST using Multivariate Temporal-Spatial GCNs;2024 IEEE International Test Conference in Asia (ITC-Asia);2024-08-18

3. Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies;ACM Transactions on Design Automation of Electronic Systems;2024-08-13

4. A Survey and Recent Advances: Machine Intelligence in Electronic Testing;Journal of Electronic Testing;2024-04

5. An Amalgamated Testability Measure Derived from Machine Intelligence;2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID);2024-01-06

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