Real-Time FPGA Investigation of Potential FEC Schemes for 800G-ZR/ZR+ Forward Error Correction
Author:
Affiliation:
1. State Key Laboratory of Mobile Network and Mobile Multimedia Technology, ZTE Corporation, Shenzhen, China
2. ZTE Corporation, Wuhan, China
Funder
National Key Research and Development Program of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Atomic and Molecular Physics, and Optics
Link
http://xplorestaging.ieee.org/ielx7/50/10027612/09935118.pdf?arnumber=9935118
Reference25 articles.
1. Investigation of Potential FEC Schemes for 800G-ZR Forward Error Correction
2. FPGA Investigation on Error-Floor Performance of a Concatenated Staircase and Hamming Code for 400G-ZR Forward Error Correction
3. Class of algorithms for decoding block codes with channel measurement information
4. Leveraging 400G ZR FEC technology;smith;Proc IEEE 802 3 Beyond 10km Opt PHYs Study Group Meeting,0
5. FEC considerations for 800ZR;sugiyama;Optical Internetworking Forum,2021
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