A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation-Reference-Cited by-同舟云学术

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A 6 Gbps PAM-3 Transceiver with Time-Varying Offset Compensation

Published:2022-11-06 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE Asian Solid-State Circuits Conference (A-SSCC)
language:
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Author:

Kim Ju Eon¹,Yoon Dong-Hyun²,Song Junyoung³,Baek Kwang-Hyun⁴,Choi Jung-Hwan¹,Kim Tony Tae-Hyoung²

Affiliation:

1. Samsung Electronics

2. Nanyang Technological University

3. Incheon National University

4. Chung-Ang University

Funder

Samsung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9980472/9980536/09980713.pdf?arnumber=9980713

Reference3 articles.

1. 22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor

2. 23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface

3. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-08

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