An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector-Reference-Cited by-同舟云学术

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An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector

Published:2007-08 Issue: Volume: Page:
ISSN:
Container-title:10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)
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Author:

Sciagura Emanuele,Zicari Paolo,Perri Stefania,Corsonello Pasquale

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4341432/4341433/04341456.pdf?arnumber=4341456

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Improved Gardner Feedback Timing Synchronization Loop;2022 10th International Conference on Intelligent Computing and Wireless Optical Communications (ICWOC);2022-06-10

2. Statistical Histogram-based Blind Frequency Offset Estimation for MPSK and MQAM Signal;2022 International Conference on Machine Learning and Knowledge Engineering (MLKE);2022-02

3. Flag Based All Digital Timing Recovery;2019 IEEE CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON);2019-11

4. A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals;Microprocessors and Microsystems;2008-11

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