Efficient Clocking Strategies for Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Implementation
Author:
Affiliation:
1. Electronics and Communication Engineering, Sree Vidyanikethan Engineering College,Tirupati,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10624684/10624740/10625097.pdf?arnumber=10625097
Reference10 articles.
1. RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems
2. Energy-Efficient Single Flux Quantum Technology
3. Ultra-low-power superconductor logic
4. 18-GHz, 4.0-aJ/bit Operation of Ultra-Low-Energy Rapid Single-Flux-Quantum Shift Registers
5. 64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure
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