Improving Soft Error Reliability of FPGA-based Deep Neural Networks with Reduced Approximate TMR-Reference-Cited by-同舟云学术

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Improving Soft Error Reliability of FPGA-based Deep Neural Networks with Reduced Approximate TMR

Published:2021-10-28 Issue: Volume: Page:
ISSN:
Container-title:2021 11th International Conference on Computer Engineering and Knowledge (ICCKE)
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Author:

Hosseinkhani Anahita¹,Ghavami Behnam¹

Affiliation:

1. Shahid Bahonar University of Kerman,Iran

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9721437/9721438/09721442.pdf?arnumber=9721442

Reference22 articles.

1. Partitioning triple modular redundancy for single event upset mitigation in FPGA;wang;2010 International Conference on E-Product E-Service and E-Entertainment ICEEE,2010

2. Gradient-based learning applied to document recognition

3. ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms

4. Robustness against SEU of an artificial neural network space application

5. SEU experiments on an Artificial Neural Network implemented by means of digital processors

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1. A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks;ACM Computing Surveys;2024-01-22

2. Kernel-as-a-Service;Proceedings of the 24th International Middleware Conference on ZZZ;2023-11-27

3. Approximate Newton method using frequency upscaling for total variation-based image denoising;2023 IEEE 3rd International Conference on Computer Systems (ICCS);2023-09-22

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