Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization-Reference-Cited by-同舟云学术

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Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

Published:2023-12-04 Issue: Volume:14 Page:1-4
ISSN:
Container-title:2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
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Author:

Guerin Mathieu¹,Haddad Fayrouz¹,Sazzad Md-Hossain¹,Kaufmann Ivan²,Hedayat Christian³,Rahajandraibe Wenceslas¹,Vauché Rémy¹,Hilleringmann Ulrich²

Affiliation:

1. Aix Marseille Université CNRS, Université de Toulon, IM2NP,Marseille,France,UMR7334

2. University of Paderborn,Germany

3. Fraunhofer ENAS,Paderborn,Germany

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10382705/10382711/10382733.pdf?arnumber=10382733

Reference21 articles.

1. Behavioral modeling of charge pump phase locked loops

2. Analog, Digital and Mixed-Signal Design Flows

3. Analysis and Design of High Order Digital Phase Locked Loops;Daniels;The National University of Ireland,2008

4. Charge-Pump Phase-Lock Loops

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