Low-cost TSV process using electroless Ni plating for 3D stacked DRAM
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5482824/5490635/05490838.pdf?arnumber=5490838
Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Research Progress of Electroless Plating Technology in Chip Manufacturing;Acta Chimica Sinica;2022
2. High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications;Japanese Journal of Applied Physics;2020-03-04
3. Fully-Filled, Highly-Reliable Fine-Pitch Interposers with TSV Aspect Ratio >10 for Future 3D-LSI/IC Packaging;2019 IEEE 69th Electronic Components and Technology Conference (ECTC);2019-05
4. (Invited) Conductive Polymer/Metal Composite for Filling of TSV;ECS Transactions;2017-08-01
5. Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects;Nanotechnology;2016-07-07
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