Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7998598/7999654/07999910.pdf?arnumber=7999910
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design and Analysis of Double-side Characteristic Impedance Compensation Structure in 2.5D / 3D Package for High-speed Serial Link;2023 IEEE Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMC+SIPI);2023-07-29
2. Invertible Neural Networks for High-Speed Channel Design & Parameter Distribution Estimation;2021 IEEE 30th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS);2021-10-17
3. Worst-Case Eye Analysis of High-Speed Channels Based on Bayesian Optimization;IEEE Transactions on Electromagnetic Compatibility;2021-02
4. IC Package Interconnect Line Characterization Based on Frequency-Variant Transmission Line Modeling and Experimental S-Parameters;IEEE Transactions on Components, Packaging and Manufacturing Technology;2019-06
5. A Hybrid Methodology for Jitter and Eye Estimation in High-Speed Serial Channels Using Polynomial Chaos Surrogate Models;IEEE Access;2019
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