Full integration of a 3D demonstrator with TSV first interposer, ultra thin die stacking and wafer level packaging-Reference-Cited by-同舟云学术

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Full integration of a 3D demonstrator with TSV first interposer, ultra thin die stacking and wafer level packaging

Published:2013-05 Issue: Volume: Page:
ISSN:
Container-title:2013 IEEE 63rd Electronic Components and Technology Conference
language:
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Author:

Pares G.,Karoui C.,Zaid A.,Dosseul F.,Feron M.,Attard A.,Klug G.,Luesebrink H.,Martinschitz K.,Launay N.,Belhenini S.,Simon G.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6573226/6575533/06575588.pdf?arnumber=6575588

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Low-Temperature Diffusion Behavior of Ti in Cu/Ti-Ti/Cu Bonding;Journal of Electronic Materials;2022-03-08

2. Low-Temperature (260 °C) Solderless Cu–Cu Bonding for Fine-Pitch 3-D Packaging and Heterogeneous Integration;IEEE Transactions on Components, Packaging and Manufacturing Technology;2021-04

3. Stress investigation of annular-trench-isolated TSV by polarized Raman spectroscopy measurement and finite element simulation;Microelectronics Reliability;2019-08

4. Validation of TSV thermo-mechanical simulation by stress measurement;Microelectronics Reliability;2016-04

5. Silicon Process and Manufacturing Technology Evolution: An overview of advancements in chip making.;IEEE Consumer Electronics Magazine;2014-07

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