Development of a stacked WCSP package platform using TSV (Through Silicon Via) technology

Author:

Dunne Rajiv,Takahashi Yoshimi,Mawatari Kazuaki,Matsuura Masamitsu,Bonifield Tom,Steinmann Philipp,Stepniak Dave

Publisher

IEEE

Cited by 12 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. On the optimization of molding warpage for wafer-level glass interposer packaging;Journal of Materials Science: Materials in Electronics;2023-04

2. FE Simulation Model for Warpage Evaluation of Glass Interposer Substrate Packages;IEEE Transactions on Components, Packaging and Manufacturing Technology;2021-04

3. Fundamentals of Solder Alloys in 3D Packaging;3D Microelectronic Packaging;2020-11-24

4. Machine-Learning Approach in Detection and Classification for Defects in TSV-Based 3-D IC;IEEE Transactions on Components, Packaging and Manufacturing Technology;2018-04

5. A Novel 3D IC Wafer-Level-Package for New Wave MEMS;2017 IEEE 67th Electronic Components and Technology Conference (ECTC);2017-05

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