Managing SRAM reliability from bitcell to library level-Reference-Cited by-同舟云学术

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Managing SRAM reliability from bitcell to library level

Published:2010 Issue: Volume: Page:
ISSN:
Container-title:2010 IEEE International Reliability Physics Symposium
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Author:

Huard Vincent,Chevallier Remy,Parthasarathy Chittoor,Mishra Anand,Ruiz-Amador Natalia,Persin Flore,Robert Vincent,Chimeno Alejandro,Pion Emmanuel,Planes Nicolas,Ney David,Cacho Florian,Kapoor Neeraj,Kulshrestha Vishal,Chopra Sanjeev,Vialle Nicolas

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5482567/5488659/05488755.pdf?arnumber=5488755

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Predicting Failure Distributions of SRAM Arrays by Using Extreme Value Statistic, Bit Cell Simulation, and Machine Learning;IEEE Transactions on Device and Materials Reliability;2023-09

2. Online NBTI-induced partially depleted (PD) SOI degradation and recovery prediction utilizing long short-term memory (LSTM);Microelectronics Reliability;2023-03

3. Pre-silicon Memory Validation;2022 IEEE 5th International Conference on Electronics and Communication Engineering (ICECE);2022-12-16

4. Modeling of NBTI Using BAT Framework: DC-AC Stress-Recovery Kinetics, Material, and Process Dependence;IEEE Transactions on Device and Materials Reliability;2020-03

5. SRAM Stability Analysis and Performance–Reliability Tradeoff for Different Cache Configurations;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-03

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