Author:
Jaiswal Kokila Bharti,Nithish Kumar V ,Seshadri Pavithra,Lakshminarayanan G
Cited by
17 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of low power Wallace tree multiplier using modified full adder;AIP Conference Proceedings;2024
2. Design of Efficient Multiply-Accumulate Unit for Convolutional Neural Networks;Journal of Physics: Conference Series;2023-10-01
3. Design and Analysis of 8-bit Vedic Multiplier;2023 5th Biennial International Conference on Nascent Technologies in Engineering (ICNTE);2023-01-20
4. High-Speed Grouping and Decomposition Multiplier for Binary Multiplication;Electronics;2022-12-16
5. Bit Wise Multipliers Using Symmetric Stackers;2022 International Conference on Power, Energy, Control and Transmission Systems (ICPECTS);2022-12-08