Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9044284/9065293/09065529.pdf?arnumber=9065529
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Watt: A Write-Optimized RRAM-Based Accelerator for Attention;Lecture Notes in Computer Science;2024
2. HyAcc: A Hybrid CAM-MAC RRAM-based Accelerator for Recommendation Model;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06
3. Static Scheduling of Weight Programming for DNN Acceleration with Resource Constrained PIM;ACM Transactions on Embedded Computing Systems;2023-08-11
4. LADDER: Architecting Content and Location-aware Writes for Crossbar Resistive Memories;MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture;2021-10-17
5. Accelerating 3D vertical resistive memories with opportunistic write latency reduction;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02
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