Performance Analysis of Dielectrically Separated Independent Gates Junctionless DG-MOSFET: A Digital Perspective
Author:
Affiliation:
1. SR University,Department of ECE,Telangana,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9828864/9828869/09828882.pdf?arnumber=9828882
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4. Optimization of Design Space for Vertically Stacked Junctionless Nanosheet FET for Analog/RF Applications;valasa;Silicon,2022
5. Design Insights into Thermal Performance of Vertically Stacked JL-NSFET with High-k Gate Dielectric for Sub 5-nm Technology Node
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