An Efficient FPGA Implementation of LDPC Decoder for 5G New Radio-Reference-Cited by-同舟云学术

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An Efficient FPGA Implementation of LDPC Decoder for 5G New Radio

Published:2023-04-19 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI)
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Author:

Devi R. Varshini¹,Rajaram S.¹

Affiliation:

1. Thiagarajar College of Engg,Dept of ECE,Madurai,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10133933/10133939/10134365.pdf?arnumber=10134365

Reference21 articles.

1. Low-Density Parity Check Code (LDPC Codes) Overview;borwankar;ArXiv Preprint,2020

2. Algebra-Assisted Construction of Quasi-Cyclic LDPC Codes for 5G New Radio;bai;IEEE Access,2018

3. Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

4. Design and FPGA Implementation of LDPC Decoder Chip for Communication System using VHDL

5. A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder

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