An Energy-Efficient Processing Element Design for Coarse-Grained Reconfigurable Architecture on FPGA-Reference-Cited by-同舟云学术

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An Energy-Efficient Processing Element Design for Coarse-Grained Reconfigurable Architecture on FPGA

Published:2022-05-13 Issue: Volume: Page:
ISSN:
Container-title:2022 11th International Conference on Communications, Circuits and Systems (ICCCAS)
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Author:

Su Lingzhi¹,Goh Wang Ling¹,Lan Jingjing²,Nambiar Vishnu P.²,Do Anh Tuan²,Bandara Thilini Kaushalya³,Mohite Aditi Kulkarni³,Wang Bo⁴

Affiliation:

1. Nanyang Technological University,School of Electrical and Electronic Engineering,639798, Singapore

2. Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR),138634, Singapore

3. National University of Singapore,Department of Computer Science,119077, Singapore

4. Singapore University of Technology and Design,Information Systems Technology and Design,487372, Singapore

Funder

National Research Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9823956/9823977/09825410.pdf?arnumber=9825410

Reference9 articles.

1. A Survey of Coarse-Grained Reconfigurable Architecture and Design: Taxonomy Challenges and Applications;liu;ACM Comput Surv,2019

2. An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks

3. HyCUBE: A 0.9V 26.4 MOPS/mW, 290 pJ/op, Power Efficient Accelerator for IoT Applications

4. HyCUBE

5. An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding

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