A 5mA 0.6¿m CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance-Reference-Cited by-同舟云学术

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A 5mA 0.6¿m CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance

Published:2007-02 Issue: Volume: Page:
ISSN:0193-6530
Container-title:2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
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Author:

Gupta Vishal,Rincon-Mora Gabriel A.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4242240/4242241/04242494.pdf?arnumber=4242494

Cited by 20 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation;Microelectronics Journal;2024-09

2. A Fast Transient Response Capless LDO Regulator Achieving -78 dB of PSR Up to 2 MHz;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. Analysis of Power-Supply-Rejection Enhancement Techniques for Low-Dropout Regulators;IEEE Access;2024

4. A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance;Integration;2023-11

5. A wide input voltage range, high power supply rejection low‐dropout regulator with a closed‐loop charge pump for sensor front‐end circuits;International Journal of Circuit Theory and Applications;2023-08-15

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