29.2 A 235mW CT 0-3 MASH ADC achieving −167dBFS/Hz NSD with 53MHz BW-Reference-Cited by-同舟云学术

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29.2 A 235mW CT 0-3 MASH ADC achieving −167dBFS/Hz NSD with 53MHz BW

Published:2014-02 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
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Author:

Dong Yunzhi,Schreier Richard,Yang Wenhua,Korrapati Sudhir,Sheikholeslami Ali

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757521.pdf?arnumber=6757521

Cited by 19 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A 15MHz-BW 82.7dB-SNDR 98.8dB-SFDR Pipelined MASH 2–2 CT DSM in 65nm CMOS;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

3. A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems;Sensors;2022-12-20

4. Wideband and Low-Power Delta-Sigma ADCs: State of the Art, Trends and Implementation Examples;ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC);2021-09-13

5. Minimizing Signal-Dependent Residue in CT Pipelined ADCs;2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS);2021-08-09

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