28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS-Reference-Cited by-同舟云学术

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28.1 A programmable 0.7-to-2.7GHz direct ΔΣ receiver in 40nm CMOS

Published:2014-02 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
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Author:

Englund Mikko,Ostman Kim B.,Viitala Olli,Kaltiokallio Mikko,Stadius Kari,Koli Kimmo,Ryynanen Jussi

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757517.pdf?arnumber=6757517

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Delta-Sigma ADC Based on Switched-Capacitor Integrator with FIR Filter Structure;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2019-03-01

2. Analysis and Design of N-Path Filter Offset Tuning in a 0.7–2.7-GHz Receiver Front-End;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-01

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