A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/5740653/5746170/05746220.pdf?arnumber=5746220
Cited by 34 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A wideband receiver front-end with low noise and high linearity by exploiting reconfigurable dual paths in 180 nm CMOS;Modern Physics Letters B;2021-02-09
2. A Wideband Dual-path Reconfigurable Receiver Front-end in 180 nm CMOS;2020 IEEE International Conference on Semiconductor Electronics (ICSE);2020-07
3. A Survey of Self-Interference in LTE-Advanced and 5G New Radio Wireless Transceivers;IEEE Transactions on Microwave Theory and Techniques;2020-03
4. A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS;Microelectronics Journal;2018-02
5. Design and analysis of a low-noise saw-less receiver front-end resistant to strong out-of-band blocker;Analog Integrated Circuits and Signal Processing;2017-09-11
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