A 40-to-800MHz Locking Multi-Phase DLL
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4242240/4242241/04242387.pdf?arnumber=4242387
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle;IEICE Transactions on Electronics;2014
2. A 1.0-V 6-b 40 MS/s time-domain flash ADC in 0.18 μm CMOS;Analog Integrated Circuits and Signal Processing;2013-09-24
3. A high-speed four-phase clock generator for low-power on-chip SerDes applications;Microelectronics Journal;2011-09
4. A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2011
5. A wide-range all digital DLL for multiphase clock generation;Microelectronics Journal;2010-07
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