16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS-Reference-Cited by-同舟云学术

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16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS

Published:2014-02 Issue: Volume: Page:
ISSN:
Container-title:2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
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Author:

Chen Gregory,Anders Mark A.,Kaul Himanshu,Satpathy Sudhir K.,Mathew Sanu K.,Hsu Steven K.,Agarwal Amit,Krishnamurthy Ram K.,Borkar Shekhar,De Vivek

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757432.pdf?arnumber=6757432

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