29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS-Reference-Cited by-同舟云学术

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29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Cao Jun,Cui Delong,Nazemi Ali,He Tim,Li Guansheng,Catli Burak,Khanpour Mehdi,Hu Kangmin,Ali Tamer,Zhang Heng,Yu Hairong,Rhew Ben,Sheng Shiwei,Shim Yonghyun,Zhang Bo,Momtaz Afshin

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870472.pdf?arnumber=7870472

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4. 22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18

5. A 135 GHz Direct-Digital 16-QAM Wireless and DWG Link;Analog Circuits and Signal Processing;2024

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