A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8304413/8310156/08310268.pdf?arnumber=8310268
Cited by 42 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme;IEEE Journal of Solid-State Circuits;2024-04
2. ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
3. Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11
4. On the Intrinsic Linearity Limitations of Single-Bit Delta Sigma Modulators;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. High-Speed and High-Performance Continuous-Time ADCs for Automotive Receivers;IEEE Open Journal of the Solid-State Circuits Society;2023
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